Department
Physics and Engineering
Location
Bethel University
Document Type
Poster
Start Date
2-25-2026 4:00 PM
End Date
2-25-2026 5:00 PM
Abstract
This project presents the design and hardware implementation of a Finite State Machine (FSM) capable of detecting the binary sequences “1001” and “1111” with full support for overlapping occurrences. The FSM was designed to operate efficiently in real time and was implemented on an Artix‑7 FPGA development board using the AMD/Xilinx Vivado Design Suite. The system processes a serial input stream and asserts a detection signal whenever either target sequence appears, even when sequences share bits across consecutive detections. The FSM architecture, state transition logic, and verification strategy were developed and validated through simulation before being deployed to hardware. Experimental results demonstrate reliable sequence detection and confirm the correctness of the state‑based design. This project illustrates the practical application of digital design principles and FPGA‑based implementation techniques for pattern recognition systems.
Recommended Citation
Tang, Shensheng and Zander, Nick, "FPGA Implementation of a Sequence Detector using a Finite State Machine" (2026). Wednesday, February 25, 2026. 15.
https://spark.bethel.edu/dayofscholarship/spring2026/spr2026/15
Included in
FPGA Implementation of a Sequence Detector using a Finite State Machine
Bethel University
This project presents the design and hardware implementation of a Finite State Machine (FSM) capable of detecting the binary sequences “1001” and “1111” with full support for overlapping occurrences. The FSM was designed to operate efficiently in real time and was implemented on an Artix‑7 FPGA development board using the AMD/Xilinx Vivado Design Suite. The system processes a serial input stream and asserts a detection signal whenever either target sequence appears, even when sequences share bits across consecutive detections. The FSM architecture, state transition logic, and verification strategy were developed and validated through simulation before being deployed to hardware. Experimental results demonstrate reliable sequence detection and confirm the correctness of the state‑based design. This project illustrates the practical application of digital design principles and FPGA‑based implementation techniques for pattern recognition systems.